////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: P.15xf
//  \   \         Application: netgen
//  /   /         Filename: line_buff_240.v
// /___/   /\     Timestamp: Fri May 10 14:28:39 2013
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -w -sim -ofmt verilog D:/Test/jrmoc_cmos/prj/ipcore_dir/tmp/_cg/line_buff_240.ngc D:/Test/jrmoc_cmos/prj/ipcore_dir/tmp/_cg/line_buff_240.v 
// Device	: 6slx45csg324-3
// Input file	: D:/Test/jrmoc_cmos/prj/ipcore_dir/tmp/_cg/line_buff_240.ngc
// Output file	: D:/Test/jrmoc_cmos/prj/ipcore_dir/tmp/_cg/line_buff_240.v
// # of Modules	: 1
// Design Name	: line_buff_240
// Xilinx        : d:\Xilinx\14.1\ISE_DS\ISE\
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module line_buff_240 (
  clk, ce, sclr, d, q
)/* synthesis syn_black_box syn_noprune=1 */;
  input clk;
  input ce;
  input sclr;
  input [7 : 0] d;
  output [7 : 0] q;
  
  // synthesis translate_off
  
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_2_92 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_1_91 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_0_90 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_2_89 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_1_88 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_0_87 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_2_86 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_1_85 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_0_84 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_2_83 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_1_82 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_0_81 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_2_80 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_1_79 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_0_78 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_2_77 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_1_76 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_0_75 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_2_74 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_1_73 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_0_72 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_2_71 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_1_70 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_0_69 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_37_68 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_27_67 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_17_66 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_07_65 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_36_64 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_26_63 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_16_62 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_06_61 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_35_60 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_25_59 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_15_58 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_05_57 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_34_56 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_24_55 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_14_54 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_04_53 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_33_52 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_23_51 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_13_50 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_03_49 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_32_48 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_22_47 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_12_46 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_02_45 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_31_44 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_21_43 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_11_42 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_01_41 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_3_40 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_2_39 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_1_38 ;
  wire \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_0_37 ;
  wire \U0/i_synth/i_bb_inst/N1 ;
  wire \U0/i_synth/i_bb_inst/N0 ;
  wire \U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[7].srl_sig<109> ;
  wire \U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[6].srl_sig<109> ;
  wire \U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[5].srl_sig<109> ;
  wire \U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[4].srl_sig<109> ;
  wire \U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[3].srl_sig<109> ;
  wire \U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[2].srl_sig<109> ;
  wire \U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[1].srl_sig<109> ;
  wire \U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[0].srl_sig<109> ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_0_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_0_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_0_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_0_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_0_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_0_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_0_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_0_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_37_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_27_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_17_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_07_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_36_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_26_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_16_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_06_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_35_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_25_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_15_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_05_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_34_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_24_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_14_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_04_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_33_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_23_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_13_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_03_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_32_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_22_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_12_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_02_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_31_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_21_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_11_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_01_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_3_Q31_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_2_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_1_Q_UNCONNECTED ;
  wire \NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_0_Q_UNCONNECTED ;
  wire [7 : 0] \U0/i_synth/i_bb_inst/f1.many_clbs.link<0> ;
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_2_92 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[7].srl_sig<109> ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_1_91 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_2_92 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_0_90 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_1_91 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_0  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [7]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[7].srl_sig_109_0_90 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_2_89 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[6].srl_sig<109> ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_1_88 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_2_89 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_0_87 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_1_88 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_0  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [6]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[6].srl_sig_109_0_87 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_2_86 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[5].srl_sig<109> ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_1_85 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_2_86 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_0_84 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_1_85 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_0  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [5]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[5].srl_sig_109_0_84 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_2_83 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[4].srl_sig<109> ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_1_82 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_2_83 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_0_81 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_1_82 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_0  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [4]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[4].srl_sig_109_0_81 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_2_80 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[3].srl_sig<109> ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_1_79 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_2_80 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_0_78 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_1_79 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_0  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [3]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[3].srl_sig_109_0_78 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_2_77 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[2].srl_sig<109> ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_1_76 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_2_77 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_0_75 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_1_76 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_0  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [2]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[2].srl_sig_109_0_75 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_2_74 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[1].srl_sig<109> ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_1_73 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_2_74 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_0_72 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_1_73 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_0  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [1]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[1].srl_sig_109_0_72 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_2_71 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[0].srl_sig<109> ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N0 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_1_70 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_2_71 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_0_69 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_1_70 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_0  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [0]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.last_clb.gen_width[0].srl_sig_109_0_69 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/f1.many_clbs.link_07  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_37_68 ),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [0])
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_37  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_27_67 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_37_68 ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_37_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_27  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_17_66 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_27_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_27_67 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_17  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_07_65 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_17_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_17_66 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_07  (
    .CLK(clk),
    .D(d[0]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_07_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_07_65 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/f1.many_clbs.link_06  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_36_64 ),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [7])
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_36  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_26_63 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_36_64 ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_36_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_26  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_16_62 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_26_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_26_63 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_16  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_06_61 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_16_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_16_62 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_06  (
    .CLK(clk),
    .D(d[7]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_06_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_06_61 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/f1.many_clbs.link_05  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_35_60 ),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [6])
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_35  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_25_59 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_35_60 ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_35_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_25  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_15_58 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_25_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_25_59 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_15  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_05_57 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_15_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_15_58 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_05  (
    .CLK(clk),
    .D(d[6]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_05_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_05_57 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/f1.many_clbs.link_04  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_34_56 ),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [5])
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_34  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_24_55 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_34_56 ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_34_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_24  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_14_54 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_24_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_24_55 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_14  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_04_53 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_14_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_14_54 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_04  (
    .CLK(clk),
    .D(d[5]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_04_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_04_53 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/f1.many_clbs.link_03  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_33_52 ),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [4])
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_33  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_23_51 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_33_52 ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_33_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_23  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_13_50 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_23_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_23_51 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_13  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_03_49 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_13_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_13_50 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_03  (
    .CLK(clk),
    .D(d[4]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_03_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_03_49 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/f1.many_clbs.link_02  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_32_48 ),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [3])
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_32  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_22_47 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_32_48 ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_32_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_22  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_12_46 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_22_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_22_47 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_12  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_02_45 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_12_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_12_46 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_02  (
    .CLK(clk),
    .D(d[3]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_02_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_02_45 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/f1.many_clbs.link_01  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_31_44 ),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [1])
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_31  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_21_43 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_31_44 ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_31_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_21  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_11_42 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_21_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_21_43 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_11  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_01_41 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_11_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_11_42 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_01  (
    .CLK(clk),
    .D(d[1]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_01_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_01_41 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  FDE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/f1.many_clbs.link_0  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_3_40 ),
    .Q(\U0/i_synth/i_bb_inst/f1.many_clbs.link<0> [2])
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_3  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_2_39 ),
    .CE(ce),
    .Q(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_3_40 ),
    .Q31(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_3_Q31_UNCONNECTED ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_2  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_1_38 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_2_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_2_39 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_1  (
    .CLK(clk),
    .D(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_0_37 ),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_1_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_1_38 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  SRLC32E #(
    .INIT ( 32'h00000000 ))
  \U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_0  (
    .CLK(clk),
    .D(d[2]),
    .CE(ce),
    .Q(\NLW_U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_0_Q_UNCONNECTED ),
    .Q31(\U0/i_synth/i_bb_inst/Mshreg_f1.many_clbs.link_0_0_37 ),
    .A({\U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 , \U0/i_synth/i_bb_inst/N1 })
  );
  VCC   \U0/i_synth/i_bb_inst/XST_VCC  (
    .P(\U0/i_synth/i_bb_inst/N1 )
  );
  GND   \U0/i_synth/i_bb_inst/XST_GND  (
    .G(\U0/i_synth/i_bb_inst/N0 )
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/gen_output_regs.output_regs/fd/output_1  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[0].srl_sig<109> ),
    .R(sclr),
    .Q(q[0])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/gen_output_regs.output_regs/fd/output_2  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[1].srl_sig<109> ),
    .R(sclr),
    .Q(q[1])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/gen_output_regs.output_regs/fd/output_3  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[2].srl_sig<109> ),
    .R(sclr),
    .Q(q[2])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/gen_output_regs.output_regs/fd/output_4  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[3].srl_sig<109> ),
    .R(sclr),
    .Q(q[3])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/gen_output_regs.output_regs/fd/output_5  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[4].srl_sig<109> ),
    .R(sclr),
    .Q(q[4])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/gen_output_regs.output_regs/fd/output_6  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[5].srl_sig<109> ),
    .R(sclr),
    .Q(q[5])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/gen_output_regs.output_regs/fd/output_7  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[6].srl_sig<109> ),
    .R(sclr),
    .Q(q[6])
  );
  FDRE #(
    .INIT ( 1'b0 ))
  \U0/i_synth/i_bb_inst/gen_output_regs.output_regs/fd/output_8  (
    .C(clk),
    .CE(ce),
    .D(\U0/i_synth/i_bb_inst/f1.many_clbs.last_clb.gen_width[7].srl_sig<109> ),
    .R(sclr),
    .Q(q[7])
  );

// synthesis translate_on

endmodule

// synthesis translate_off

`ifndef GLBL
`define GLBL

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule

`endif

// synthesis translate_on
